These are the a lot of accepted means of implementing an cyberbanking ADC:
A direct-conversion ADC or beam ADC has a coffer of comparators sampling the ascribe arresting in parallel, anniversary battlefront for their decoded voltage range. The comparator coffer feeds a argumentation ambit that generates a cipher for anniversary voltage range. Direct about-face is actual fast, able of gigahertz sampling rates, but usually has alone 8 $.25 of resolution or fewer, aback the amount of comparators needed, 2N - 1, doubles with anniversary added bit, acute a large, big-ticket circuit. ADCs of this blazon accept a ample die size, a top ascribe capacitance, top ability dissipation, and are decumbent to aftermath glitches at the achievement (by outputting an out-of-sequence code). Scaling to newer submicrometre technologies does not advice as the accessory conflict is the ascendant architecture limitation. They are generally acclimated for video, wideband communications or added fast signals in optical storage.
A successive-approximation ADC uses a comparator to successively attenuated a ambit that contains the ascribe voltage. At anniversary alternating step, the advocate compares the ascribe voltage to the achievement of an centralized agenda to analog advocate which ability represent the mean of a alleged voltage range. At anniversary footfall in this process, the approximation is stored in a alternating approximation annals (SAR). For example, accede an ascribe voltage of 6.3 V and the antecedent ambit is 0 to 16 V. For the aboriginal step, the ascribe 6.3 V is compared to 8 V (the mean of the 0–16 V range). The comparator letters that the ascribe voltage is beneath than 8 V, so the SAR is adapted to attenuated the ambit to 0–8 V. For the additional step, the ascribe voltage is compared to 4 V (midpoint of 0–8). The comparator letters the ascribe voltage is aloft 4 V, so the SAR is adapted to reflect the ascribe voltage is in the ambit 4–8 V. For the third step, the ascribe voltage is compared with 6 V (halfway amid 4 V and 8 V); the comparator letters the ascribe voltage is greater than 6 volts, and seek ambit becomes 6–8 V. The accomplish are connected until the adapted resolution is reached.
A ramp-compare ADC produces a saw-tooth arresting that ramps up or down again bound allotment to zero. If the access starts, a timer starts counting. If the access voltage matches the input, a comparator fires, and the timer's amount is recorded. Timed access converters crave the atomic amount of transistors. The access time is acute to temperature because the ambit breeding the access is generally just some simple oscillator. There are two solutions: use a clocked adverse active a DAC and again use the comparator to bottle the counter's value, or calibrate the timed ramp. A appropriate advantage of the ramp-compare arrangement is that comparing a additional arresting just requires accession comparator, and accession annals to abundance the voltage value. A actual simple (non-linear) ramp-converter can be implemented with a microcontroller and one resistor and capacitor.9 Vice versa, a abounding capacitor can be taken from an integrator, time-to-amplitude converter, appearance detector, sample and authority circuit, or aiguille and authority ambit and discharged. This has the advantage that a apathetic comparator cannot be abashed by fast ascribe changes.
The Wilkinson ADC was advised by D. H. Wilkinson in 1950. The Wilkinson ADC is based on the allegory of an ascribe voltage with that produced by a charging capacitor. The capacitor is accustomed to allegation until its voltage is according to the amplitude of the ascribe beating (a comparator determines if this action has been reached). Then, the capacitor is accustomed to acquittal linearly, which produces a access voltage. At the point if the capacitor begins to discharge, a aboideau beating is initiated. The aboideau beating charcoal on until the capacitor is absolutely discharged. Appropriately the continuance of the aboideau beating is anon proportional to the amplitude of the ascribe pulse. This aboideau beating operates a beeline aboideau which receives pulses from a high-frequency oscillator clock. While the aboideau is open, a detached amount of alarm pulses canyon through the beeline aboideau and are counted by the abode register. The time the beeline aboideau is accessible is proportional to the amplitude of the ascribe pulse, appropriately the amount of alarm pulses recorded in the abode annals is proportional also. Alternatively, the charging of the capacitor could be monitored, rather than the discharge.1011
An amalgam ADC (also dual-slope or multi-slope ADC) applies the alien ascribe voltage to the ascribe of an integrator and allows the voltage to access for a anchored time aeon (the countdown period). Again a accepted advertence voltage of adverse polarity is activated to the integrator and is accustomed to access until the integrator achievement allotment to aught (the abandoned period). The ascribe voltage is computed as a action of the advertence voltage, the connected countdown time period, and the abstinent abandoned time period. The abandoned time altitude is usually fabricated in units of the converter's clock, so best affiliation times acquiesce for college resolutions. Likewise, the acceleration of the advocate can be bigger by sacrificing resolution. Converters of this blazon (or variations on the concept) are acclimated in a lot of agenda voltmeters for their breadth and flexibility.
A delta-encoded ADC or counter-ramp has an up-down adverse that feeds a agenda to analog advocate (DAC). The ascribe arresting and the DAC both go to a comparator. The comparator controls the counter. The ambit uses abrogating acknowledgment from the comparator to acclimatize the adverse until the DAC's achievement is abutting abundant to the ascribe signal. The amount is apprehend from the counter. Basin converters accept actual advanced ranges and top resolution, but the about-face time is abased on the ascribe arresting level, admitting it will consistently accept a affirmed worst-case. Basin converters are generally actual acceptable choices to apprehend real-world signals. A lot of signals from concrete systems do not change abruptly. Some converters amalgamate the basin and alternating approximation approaches; this works abnormally able-bodied if top frequencies are accepted to be baby in magnitude.
A activity ADC (also alleged subranging quantizer) uses two or added accomplish of subranging. First, a base about-face is done. In a additional step, the aberration to the ascribe arresting is bent with a agenda to analog advocate (DAC). This aberration is again adapted finer, and the after-effects are accumulated in a endure step. This can be advised a clarification of the successive-approximation ADC wherein the acknowledgment advertence arresting consists of the acting about-face of a accomplished ambit of $.25 (for example, four bits) rather than just the next-most-significant bit. By accumulation the claim of the alternating approximation and beam ADCs this blazon is fast, has a top resolution, and alone requires a baby die size.
A sigma-delta ADC (also accepted as a delta-sigma ADC) oversamples the adapted arresting by a ample agency and filters the adapted arresting band. Generally, a abate amount of $.25 than appropriate are adapted application a Beam ADC afterwards the filter. The consistent signal, forth with the absurdity generated by the detached levels of the Flash, is fed aback and subtracted from the ascribe to the filter. This abrogating acknowledgment has the aftereffect of babble abstraction the absurdity due to the Beam so that it does not arise in the adapted arresting frequencies. A agenda clarify (decimation filter) follows the ADC which reduces the sampling rate, filters off exceptionable babble arresting and increases the resolution of the achievement (sigma-delta modulation, aswell alleged delta-sigma modulation).
A time-interleaved ADC uses M alongside ADCs area anniversary ADC samples abstracts every M:th aeon of the able sample clock. The aftereffect is that the sample amount is added M times compared to what anniversary alone ADC can manage. In practice, the alone differences amid the M ADCs abase the all-embracing achievement abbreviation the SFDR12. However, technologies abide to actual for these time-interleaving conflict errors.
An ADC with average FM date aboriginal uses a voltage-to-frequency advocate to catechumen the adapted arresting into an aquiver arresting with a abundance proportional to the voltage of the adapted signal, and again uses a abundance adverse to catechumen that abundance into a agenda calculation proportional to the adapted arresting voltage. Best affiliation times acquiesce for college resolutions. Likewise, the acceleration of the advocate can be bigger by sacrificing resolution. The two locations of the ADC may be broadly separated, with the abundance arresting anesthetized through an opto-isolator or transmitted wirelessly. Some such ADCs use sine beachcomber or aboveboard beachcomber abundance modulation; others use pulse-frequency modulation. Such ADCs were already the a lot of accepted way to appearance a agenda affectation of the cachet of a limited analog sensor.1314151617
There can be added ADCs that use a aggregate of electronics and added technologies:
A time-stretch analog-to-digital advocate (TS-ADC) digitizes a actual advanced bandwidth analog signal, that cannot be digitized by a accepted cyberbanking ADC, by time-stretching the arresting above-mentioned to digitization. It frequently uses a photonic preprocessor frontend to time-stretch the signal, which finer slows the arresting down in time and compresses its bandwidth. As a result, an cyberbanking backend ADC, that would accept been too apathetic to abduction the aboriginal signal, can now abduction this slowed down signal. For connected abduction of the signal, the frontend aswell divides the arresting into assorted segments in accession to time-stretching. Anniversary articulation is alone digitized by a abstracted cyberbanking ADC. Finally, a agenda arresting processor rearranges the samples and removes any distortions added by the frontend to crop the bifold abstracts that is the agenda representation of the aboriginal analog signal.
A direct-conversion ADC or beam ADC has a coffer of comparators sampling the ascribe arresting in parallel, anniversary battlefront for their decoded voltage range. The comparator coffer feeds a argumentation ambit that generates a cipher for anniversary voltage range. Direct about-face is actual fast, able of gigahertz sampling rates, but usually has alone 8 $.25 of resolution or fewer, aback the amount of comparators needed, 2N - 1, doubles with anniversary added bit, acute a large, big-ticket circuit. ADCs of this blazon accept a ample die size, a top ascribe capacitance, top ability dissipation, and are decumbent to aftermath glitches at the achievement (by outputting an out-of-sequence code). Scaling to newer submicrometre technologies does not advice as the accessory conflict is the ascendant architecture limitation. They are generally acclimated for video, wideband communications or added fast signals in optical storage.
A successive-approximation ADC uses a comparator to successively attenuated a ambit that contains the ascribe voltage. At anniversary alternating step, the advocate compares the ascribe voltage to the achievement of an centralized agenda to analog advocate which ability represent the mean of a alleged voltage range. At anniversary footfall in this process, the approximation is stored in a alternating approximation annals (SAR). For example, accede an ascribe voltage of 6.3 V and the antecedent ambit is 0 to 16 V. For the aboriginal step, the ascribe 6.3 V is compared to 8 V (the mean of the 0–16 V range). The comparator letters that the ascribe voltage is beneath than 8 V, so the SAR is adapted to attenuated the ambit to 0–8 V. For the additional step, the ascribe voltage is compared to 4 V (midpoint of 0–8). The comparator letters the ascribe voltage is aloft 4 V, so the SAR is adapted to reflect the ascribe voltage is in the ambit 4–8 V. For the third step, the ascribe voltage is compared with 6 V (halfway amid 4 V and 8 V); the comparator letters the ascribe voltage is greater than 6 volts, and seek ambit becomes 6–8 V. The accomplish are connected until the adapted resolution is reached.
A ramp-compare ADC produces a saw-tooth arresting that ramps up or down again bound allotment to zero. If the access starts, a timer starts counting. If the access voltage matches the input, a comparator fires, and the timer's amount is recorded. Timed access converters crave the atomic amount of transistors. The access time is acute to temperature because the ambit breeding the access is generally just some simple oscillator. There are two solutions: use a clocked adverse active a DAC and again use the comparator to bottle the counter's value, or calibrate the timed ramp. A appropriate advantage of the ramp-compare arrangement is that comparing a additional arresting just requires accession comparator, and accession annals to abundance the voltage value. A actual simple (non-linear) ramp-converter can be implemented with a microcontroller and one resistor and capacitor.9 Vice versa, a abounding capacitor can be taken from an integrator, time-to-amplitude converter, appearance detector, sample and authority circuit, or aiguille and authority ambit and discharged. This has the advantage that a apathetic comparator cannot be abashed by fast ascribe changes.
The Wilkinson ADC was advised by D. H. Wilkinson in 1950. The Wilkinson ADC is based on the allegory of an ascribe voltage with that produced by a charging capacitor. The capacitor is accustomed to allegation until its voltage is according to the amplitude of the ascribe beating (a comparator determines if this action has been reached). Then, the capacitor is accustomed to acquittal linearly, which produces a access voltage. At the point if the capacitor begins to discharge, a aboideau beating is initiated. The aboideau beating charcoal on until the capacitor is absolutely discharged. Appropriately the continuance of the aboideau beating is anon proportional to the amplitude of the ascribe pulse. This aboideau beating operates a beeline aboideau which receives pulses from a high-frequency oscillator clock. While the aboideau is open, a detached amount of alarm pulses canyon through the beeline aboideau and are counted by the abode register. The time the beeline aboideau is accessible is proportional to the amplitude of the ascribe pulse, appropriately the amount of alarm pulses recorded in the abode annals is proportional also. Alternatively, the charging of the capacitor could be monitored, rather than the discharge.1011
An amalgam ADC (also dual-slope or multi-slope ADC) applies the alien ascribe voltage to the ascribe of an integrator and allows the voltage to access for a anchored time aeon (the countdown period). Again a accepted advertence voltage of adverse polarity is activated to the integrator and is accustomed to access until the integrator achievement allotment to aught (the abandoned period). The ascribe voltage is computed as a action of the advertence voltage, the connected countdown time period, and the abstinent abandoned time period. The abandoned time altitude is usually fabricated in units of the converter's clock, so best affiliation times acquiesce for college resolutions. Likewise, the acceleration of the advocate can be bigger by sacrificing resolution. Converters of this blazon (or variations on the concept) are acclimated in a lot of agenda voltmeters for their breadth and flexibility.
A delta-encoded ADC or counter-ramp has an up-down adverse that feeds a agenda to analog advocate (DAC). The ascribe arresting and the DAC both go to a comparator. The comparator controls the counter. The ambit uses abrogating acknowledgment from the comparator to acclimatize the adverse until the DAC's achievement is abutting abundant to the ascribe signal. The amount is apprehend from the counter. Basin converters accept actual advanced ranges and top resolution, but the about-face time is abased on the ascribe arresting level, admitting it will consistently accept a affirmed worst-case. Basin converters are generally actual acceptable choices to apprehend real-world signals. A lot of signals from concrete systems do not change abruptly. Some converters amalgamate the basin and alternating approximation approaches; this works abnormally able-bodied if top frequencies are accepted to be baby in magnitude.
A activity ADC (also alleged subranging quantizer) uses two or added accomplish of subranging. First, a base about-face is done. In a additional step, the aberration to the ascribe arresting is bent with a agenda to analog advocate (DAC). This aberration is again adapted finer, and the after-effects are accumulated in a endure step. This can be advised a clarification of the successive-approximation ADC wherein the acknowledgment advertence arresting consists of the acting about-face of a accomplished ambit of $.25 (for example, four bits) rather than just the next-most-significant bit. By accumulation the claim of the alternating approximation and beam ADCs this blazon is fast, has a top resolution, and alone requires a baby die size.
A sigma-delta ADC (also accepted as a delta-sigma ADC) oversamples the adapted arresting by a ample agency and filters the adapted arresting band. Generally, a abate amount of $.25 than appropriate are adapted application a Beam ADC afterwards the filter. The consistent signal, forth with the absurdity generated by the detached levels of the Flash, is fed aback and subtracted from the ascribe to the filter. This abrogating acknowledgment has the aftereffect of babble abstraction the absurdity due to the Beam so that it does not arise in the adapted arresting frequencies. A agenda clarify (decimation filter) follows the ADC which reduces the sampling rate, filters off exceptionable babble arresting and increases the resolution of the achievement (sigma-delta modulation, aswell alleged delta-sigma modulation).
A time-interleaved ADC uses M alongside ADCs area anniversary ADC samples abstracts every M:th aeon of the able sample clock. The aftereffect is that the sample amount is added M times compared to what anniversary alone ADC can manage. In practice, the alone differences amid the M ADCs abase the all-embracing achievement abbreviation the SFDR12. However, technologies abide to actual for these time-interleaving conflict errors.
An ADC with average FM date aboriginal uses a voltage-to-frequency advocate to catechumen the adapted arresting into an aquiver arresting with a abundance proportional to the voltage of the adapted signal, and again uses a abundance adverse to catechumen that abundance into a agenda calculation proportional to the adapted arresting voltage. Best affiliation times acquiesce for college resolutions. Likewise, the acceleration of the advocate can be bigger by sacrificing resolution. The two locations of the ADC may be broadly separated, with the abundance arresting anesthetized through an opto-isolator or transmitted wirelessly. Some such ADCs use sine beachcomber or aboveboard beachcomber abundance modulation; others use pulse-frequency modulation. Such ADCs were already the a lot of accepted way to appearance a agenda affectation of the cachet of a limited analog sensor.1314151617
There can be added ADCs that use a aggregate of electronics and added technologies:
A time-stretch analog-to-digital advocate (TS-ADC) digitizes a actual advanced bandwidth analog signal, that cannot be digitized by a accepted cyberbanking ADC, by time-stretching the arresting above-mentioned to digitization. It frequently uses a photonic preprocessor frontend to time-stretch the signal, which finer slows the arresting down in time and compresses its bandwidth. As a result, an cyberbanking backend ADC, that would accept been too apathetic to abduction the aboriginal signal, can now abduction this slowed down signal. For connected abduction of the signal, the frontend aswell divides the arresting into assorted segments in accession to time-stretching. Anniversary articulation is alone digitized by a abstracted cyberbanking ADC. Finally, a agenda arresting processor rearranges the samples and removes any distortions added by the frontend to crop the bifold abstracts that is the agenda representation of the aboriginal analog signal.
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