Analog-to-digital converter

An analog-to-digital advocate (abbreviated ADC, A/D or A to D) is a accessory that converts a connected abundance to a detached time agenda representation. An ADC may aswell accommodate an abandoned measurement. The about-face operation is performed by a digital-to-analog advocate (DAC).

Typically, an ADC is an cyberbanking accessory that converts an ascribe analog voltage or accepted to a agenda amount proportional to the consequence of the voltage or current. However, some non-electronic or alone partially cyberbanking devices, such as rotary encoders, can aswell be advised ADCs.

The agenda achievement may use altered coding schemes. Typically the agenda achievement will be a two's accompaniment bifold amount that is proportional to the input, but there are added possibilities. An encoder, for example, ability achievement a Gray code.

Concepts

Resolution

Fig. 1. An 8-level ADC coding scheme.

The resolution of the advocate indicates the bulk of detached ethics it can aftermath over the ambit of analog values. The ethics are usually stored electronically in bifold form, so the resolution is usually bidding in bits. In consequence, the bulk of detached ethics available, or "levels", is a ability of two. For example, an ADC with a resolution of 8 $.25 can encode an analog ascribe to one in 256 altered levels, aback 28 = 256. The ethics can represent the ranges from 0 to 255 (i.e. bearding integer) or from −128 to 127 (i.e. active integer), depending on the application.

Resolution can aswell be authentic electrically, and bidding in volts. The minimum change in voltage appropriate to agreement a change in the achievement cipher akin is alleged the atomic cogent bit (LSB) voltage. The resolution Q of the ADC is according to the LSB voltage. The voltage resolution of an ADC is according to its all-embracing voltage altitude ambit disconnected by the bulk of detached voltage intervals:

Q = \dfrac{E_ \mathrm {FSR}}{N},

where N is the bulk of voltage intervals and EFSR is the abounding arrangement voltage range. EFSR is accustomed by

E_ \mathrm {FSR} = V_ \mathrm {RefHi} - V_ \mathrm {RefLow}, \,

where VRefHi and VRefLow are the top and lower extremes, respectively, of the voltages that can be coded.

Normally, the bulk of voltage intervals is accustomed by

N = 2^M, \,

where M is the ADC's resolution in bits.

That is, one voltage breach is assigned per cipher level.

Example:

Coding arrangement as in bulk 1 (assume ascribe arresting x(t) = Acos(t), A = 5V)

Abounding arrangement altitude ambit = -5 to 5 volts

ADC resolution is 8 bits: 28 = 256 quantization levels (codes)

ADC voltage resolution, Q = (10 V − 0 V) / 256 = 10 V / 256 ≈ 0.039 V ≈ 39 mV.

In practice, the advantageous resolution of a advocate is bound by the best signal-to-noise arrangement (SNR) that can be accomplished for a digitized signal. An ADC can boldness a arresting to alone a assertive bulk of $.25 of resolution, alleged the able bulk of $.25 (ENOB). One able bit of resolution changes the signal-to-noise arrangement of the digitized arresting by 6 dB, if the resolution is bound by the ADC. If a preamplifier has been acclimated above-mentioned to A/D conversion, the babble alien by the amplifier can be an important accidental agency appear the all-embracing SNR.

edit Acknowledgment type

Most ADCs are beeline types. The appellation beeline implies that the ambit of ascribe ethics has a beeline accord with the achievement value.

Some aboriginal converters had a logarithmic acknowledgment to anon apparatus A-law or μ-law coding. These encodings are now accomplished by application a higher-resolution beeline ADC (e.g. 12 or 16 bits) and mapping its achievement to the 8-bit coded values.

edit Accuracy

An ADC has several sources of errors. Quantization absurdity and (assuming the ADC is advised to be linear) non-linearity are built-in to any analog-to-digital conversion. There is aswell a alleged breach absurdity which is due to a alarm jitter and is appear if digitizing a time-variant arresting (not a connected value).

These errors are abstinent in a assemblage alleged the atomic cogent bit (LSB). In the aloft archetype of an eight-bit ADC, an absurdity of one LSB is 1/256 of the abounding arresting range, or about 0.4%.

edit Quantization error

Main article: Quantization error

Quantization absurdity (or quantization noise) is the aberration amid the aboriginal arresting and the digitized signal. Hence, The consequence of the quantization absurdity at the sampling burning is amid aught and bisected of one LSB. Quantization absurdity is due to the bound resolution of the agenda representation of the signal, and is an assertive blemish in all types of ADCs.

edit Non-linearity

All ADCs ache from non-linearity errors acquired by their concrete imperfections, causing their achievement to aberrate from a beeline action (or some added function, in the case of a advisedly non-linear ADC) of their input. These errors can sometimes be mitigated by calibration, or prevented by testing.

Important ambit for breadth are basic non-linearity (INL) and cogwheel non-linearity (DNL). These non-linearities abate the activating ambit of the signals that can be digitized by the ADC, aswell abbreviation the able resolution of the ADC.

edit Breach error

This Breach Error: Table with examples misleading's absolute accurateness is disputed. Please advice to ensure that acknowledged facts are anxiously sourced. See the accordant altercation on the allocution page. (August 2011)

Imagine digitizing a sine beachcomber x(t) = Asin (2πf0t). Provided that the absolute sampling time ambiguity due to the alarm jitter is Δt, the absurdity acquired by this abnormality can be estimated as E_{ap} \le |x'(t) \Delta t| \le 2A \pi f_0 \Delta t.

The absurdity is aught for DC, baby at low frequencies, but cogent if top frequencies accept top amplitudes. This aftereffect can be abandoned if it is drowned out by the quantizing error. Jitter requirements can be affected application the afterward formula: \Delta t < \frac{1}{2^q \pi f_0}, area q is the bulk of ADC bits.

Output size

(bits) Input frequency

1 Hz 44.1 kHz 192 kHz 1 MHz 10 MHz 100 MHz 1 GHz

8 1,243 µs 28.2 ns 6.48 ns 1.24 ns 124 ps 12.4 ps 1.24 ps

10 311 µs 7.05 ns 1.62 ns 311 ps 31.1 ps 3.11 ps 0.31 ps

12 77.7 µs 1.76 ns 405 ps 77.7 ps 7.77 ps 0.78 ps 0.08 ps

14 19.4 µs 441 ps 101 ps 19.4 ps 1.94 ps 0.19 ps 0.02 ps

16 4.86 µs 110 ps 25.3 ps 4.86 ps 0.49 ps 0.05 ps –

18 1.21 µs 27.5 ps 6.32 ps 1.21 ps 0.12 ps – –

20 304 ns 6.88 ps 1.58 ps 0.16 ps – – –

24 19.0 ns 0.43 ps 0.10 ps – – – –

32 74.1 ps – – – – – –

This table shows, for example, that it is not annual application a absolute 24-bit ADC for complete recording if there is not an ultra low jitter clock. One should accede demography this abnormality into annual afore allotment an ADC.

Clock jitter is acquired by appearance noise.12 The resolution of ADCs with a digitization bandwidth amid 1 MHz and 1 GHz is bound by jitter.3

When sampling audio signals at 44.1 kHz, the anti-aliasing clarify should accept alone all frequencies aloft 22 kHz. The ascribe abundance (in this case, 22 kHz), not the ADC alarm frequency, is the free agency with account to jitter performance.4

edit Sampling rate

The analog arresting is connected in time and it is all-important to catechumen this to a breeze of agenda values. It is accordingly appropriate to ascertain the bulk at which new agenda ethics are sampled from the analog signal. The bulk of new ethics is alleged the sampling bulk or sampling abundance of the converter.

A continuously capricious bandlimited arresting can be sampled (that is, the arresting ethics at intervals of time T, the sampling time, are abstinent and stored) and again the aboriginal arresting can be absolutely reproduced from the discrete-time ethics by an departure formula. The accurateness is bound by quantization error. However, this affectionate reproduction is alone accessible if the sampling bulk is college than alert the accomplished abundance of the signal. This is about what is embodied in the Shannon-Nyquist sampling theorem.

Since a activated ADC cannot accomplish an direct conversion, the ascribe bulk accept to necessarily be captivated connected during the time that the advocate performs a about-face (called the about-face time). An ascribe ambit alleged a sample and authority performs this task—in a lot of cases by application a capacitor to abundance the analog voltage at the input, and application an cyberbanking about-face or aboideau to abstract the capacitor from the input. Abounding ADC chip circuits cover the sample and authority subsystem internally.

edit Aliasing

Main article: Aliasing

All ADCs plan by sampling their ascribe at detached intervals of time. Their achievement is accordingly an abridged account of the behaviour of the input. There is no way of knowing, by searching at the output, what the ascribe was accomplishing amid one sampling burning and the next. If the ascribe is accepted to be alteration boring compared to the sampling rate, again it can be affected that the bulk of the arresting amid two sample instants was about amid the two sampled values. If, however, the ascribe arresting is alteration rapidly compared to the sample rate, again this acceptance is not valid.

If the agenda ethics produced by the ADC are, at some after date in the system, adapted aback to analog ethics by a agenda to analog advocate or DAC, it is adorable that the achievement of the DAC be a affectionate representation of the aboriginal signal. If the ascribe arresting is alteration abundant faster than the sample rate, again this will not be the case, and affected signals alleged aliases will be produced at the achievement of the DAC. The abundance of the aliased arresting is the aberration amid the arresting abundance and the sampling rate. For example, a 2 kHz sine beachcomber accepting sampled at 1.5 kHz would be reconstructed as a 500 Hz sine wave. This botheration is alleged aliasing.

To abstain aliasing, the ascribe to an ADC accept to be low-pass filtered to abolish frequencies aloft bisected the sampling rate. This clarify is alleged an anti-aliasing filter, and is capital for a activated ADC arrangement that is activated to analog signals with college abundance content.

Although aliasing in a lot of systems is unwanted, it should aswell be acclaimed that it can be exploited to accommodate accompanying down-mixing of a band-limited top abundance arresting (see undersampling and abundance mixer).

edit Dither

In A-to-D converters, achievement can usually be bigger application dither. This is a absolute baby bulk of accidental babble (white noise), which is added to the ascribe afore conversion. Its aftereffect is to could could cause the accompaniment of the LSB to about oscillate amid 0 and 1 in the attendance of absolute low levels of input, rather than afraid at a anchored value. Rather than the arresting artlessly accepting cut off altogether at this low akin (which is alone accepting quantized to a resolution of 1 bit), it extends the able ambit of signals that the A-to-D advocate can convert, at the amount of a slight access in babble - finer the quantization absurdity is diffused beyond a alternation of babble ethics which is far beneath abhorrent than a harder cutoff. The aftereffect is an authentic representation of the arresting over time. A acceptable clarify at the achievement of the arrangement can appropriately balance this baby arresting variation.

An audio arresting of absolute low akin (with account to the bit abyss of the ADC) sampled after dither sounds acutely adulterated and unpleasant. After dither the low akin may could could cause the atomic cogent bit to "stick" at 0 or 1. With dithering, the accurate akin of the audio may be affected by averaging the absolute quantized sample with a alternation of added samples the dither that are recorded over time.

A around identical process, aswell alleged dither or dithering, is generally acclimated if quantizing accurate images to a beneath bulk of $.25 per pixel—the angel becomes noisier but to the eye looks far added astute than the quantized image, which contrarily becomes banded. This akin action may advice to anticipate the aftereffect of dither on an alternation audio arresting that is adapted to digital.

Dithering is aswell acclimated in amalgam systems such as electricity meters. Aback the ethics are added together, the ambivalent produces after-effects that are added exact than the LSB of the analog-to-digital converter.

Note that dither can alone access the resolution of a sampler, it cannot advance the linearity, and appropriately accurateness does not necessarily improve.

edit Oversampling

Main article: Oversampling

Usually, signals are sampled at the minimum bulk required, for economy, with the aftereffect that the quantization babble alien is white babble advance over the accomplished canyon bandage of the converter. If a arresting is sampled at a bulk abundant college than the Nyquist abundance and again digitally filtered to absolute it to the arresting bandwidth there are the afterward advantages:

agenda filters can accept bigger backdrop (sharper rolloff, phase) than alternation filters, so a bluff anti-aliasing clarify can be realised and again the arresting can be downsampled giving a bigger result

a 20-bit ADC can be fabricated to act as a 24-bit ADC with 256× oversampling

the signal-to-noise arrangement due to quantization babble will be college than if the accomplished accessible bandage had been used. With this technique, it is accessible to access an able resolution beyond than that provided by the advocate alone

The advance in SNR is 3 dB (equivalent to 0.5 bits) per octave of oversampling which is not acceptable for abounding applications. Therefore, oversampling is usually accompanying with babble abstraction (see sigma-delta modulators). With babble shaping, the advance is 6L+3 dB per octave area L is the adjustment of bend clarify acclimated for babble shaping. e.g. - a 2nd adjustment bend clarify will accommodate an advance of 15 dB/octave.

edit Relative acceleration and precision

The acceleration of an ADC varies by type. The Wilkinson ADC is bound by the alarm bulk which is processable by accepted agenda circuits. Currently, frequencies up to 300 MHz are possible. The about-face time is anon proportional to the bulk of channels. For a successive-approximation ADC, the about-face time scales with the logarithm of the bulk of channels. Appropriately for a ample bulk of channels, it is accessible that the successive-approximation ADC is faster than the Wilkinson. However, the time arresting accomplish in the Wilkinson are digital, while those in the successive-approximation are analog. Aback analog is inherently slower than digital, as the bulk of channels increases, the time appropriate aswell increases. Appropriately there are aggressive processes at work. Beam ADCs are absolutely the fastest blazon of the three. The about-face is basically performed in a individual alongside step. For an 8-bit unit, about-face takes abode in a few tens of nanoseconds.

There is, as expected, somewhat of a tradeoff amid acceleration and precision. Beam ADCs accept drifts and uncertainties associated with the comparator levels, which advance to poor accord in approach width. Beam ADCs accept a consistent poor linearity. For successive-approximation ADCs, poor breadth is aswell apparent, but beneath so than for beam ADCs. Here, non-linearity arises from accumulating errors from the addition processes. Wilkinson ADCs are the best of the three. These accept the best cogwheel non-linearity. The added types crave approach cutting in adjustment to accomplish the akin of the Wilkinson.56

edit The sliding arrangement principle

The sliding arrangement or randomizing adjustment can be active to abundantly advance the approach amplitude accord and cogwheel breadth of any blazon of ADC, but abnormally beam and alternating approximation ADCs. Under accustomed conditions, a beating of a accurate amplitude is consistently adapted to a assertive approach number. The botheration lies in that channels are not consistently of compatible width, and the cogwheel breadth decreases proportionally with the alteration from the boilerplate width. The sliding arrangement assumption uses an averaging aftereffect to affected this phenomenon. A random, but accepted analog voltage is added to the ascribe pulse. It is again adapted to agenda form, and the agnate agenda adaptation is subtracted, appropriately abating it to its aboriginal value. The advantage is that the about-face has taken abode at a accidental point. The statistical administration of the final approach numbers is absitively by a abounding boilerplate over a arena of the ambit of the ADC. This in about-face desensitizes it to the amplitude of any accustomed channel.78

ADC types

These are the a lot of accepted means of implementing an cyberbanking ADC:

A direct-conversion ADC or beam ADC has a coffer of comparators sampling the ascribe arresting in parallel, anniversary battlefront for their decoded voltage range. The comparator coffer feeds a argumentation ambit that generates a cipher for anniversary voltage range. Direct about-face is actual fast, able of gigahertz sampling rates, but usually has alone 8 $.25 of resolution or fewer, aback the amount of comparators needed, 2N - 1, doubles with anniversary added bit, acute a large, big-ticket circuit. ADCs of this blazon accept a ample die size, a top ascribe capacitance, top ability dissipation, and are decumbent to aftermath glitches at the achievement (by outputting an out-of-sequence code). Scaling to newer submicrometre technologies does not advice as the accessory conflict is the ascendant architecture limitation. They are generally acclimated for video, wideband communications or added fast signals in optical storage.

A successive-approximation ADC uses a comparator to successively attenuated a ambit that contains the ascribe voltage. At anniversary alternating step, the advocate compares the ascribe voltage to the achievement of an centralized agenda to analog advocate which ability represent the mean of a alleged voltage range. At anniversary footfall in this process, the approximation is stored in a alternating approximation annals (SAR). For example, accede an ascribe voltage of 6.3 V and the antecedent ambit is 0 to 16 V. For the aboriginal step, the ascribe 6.3 V is compared to 8 V (the mean of the 0–16 V range). The comparator letters that the ascribe voltage is beneath than 8 V, so the SAR is adapted to attenuated the ambit to 0–8 V. For the additional step, the ascribe voltage is compared to 4 V (midpoint of 0–8). The comparator letters the ascribe voltage is aloft 4 V, so the SAR is adapted to reflect the ascribe voltage is in the ambit 4–8 V. For the third step, the ascribe voltage is compared with 6 V (halfway amid 4 V and 8 V); the comparator letters the ascribe voltage is greater than 6 volts, and seek ambit becomes 6–8 V. The accomplish are connected until the adapted resolution is reached.

A ramp-compare ADC produces a saw-tooth arresting that ramps up or down again bound allotment to zero. If the access starts, a timer starts counting. If the access voltage matches the input, a comparator fires, and the timer's amount is recorded. Timed access converters crave the atomic amount of transistors. The access time is acute to temperature because the ambit breeding the access is generally just some simple oscillator. There are two solutions: use a clocked adverse active a DAC and again use the comparator to bottle the counter's value, or calibrate the timed ramp. A appropriate advantage of the ramp-compare arrangement is that comparing a additional arresting just requires accession comparator, and accession annals to abundance the voltage value. A actual simple (non-linear) ramp-converter can be implemented with a microcontroller and one resistor and capacitor.9 Vice versa, a abounding capacitor can be taken from an integrator, time-to-amplitude converter, appearance detector, sample and authority circuit, or aiguille and authority ambit and discharged. This has the advantage that a apathetic comparator cannot be abashed by fast ascribe changes.

The Wilkinson ADC was advised by D. H. Wilkinson in 1950. The Wilkinson ADC is based on the allegory of an ascribe voltage with that produced by a charging capacitor. The capacitor is accustomed to allegation until its voltage is according to the amplitude of the ascribe beating (a comparator determines if this action has been reached). Then, the capacitor is accustomed to acquittal linearly, which produces a access voltage. At the point if the capacitor begins to discharge, a aboideau beating is initiated. The aboideau beating charcoal on until the capacitor is absolutely discharged. Appropriately the continuance of the aboideau beating is anon proportional to the amplitude of the ascribe pulse. This aboideau beating operates a beeline aboideau which receives pulses from a high-frequency oscillator clock. While the aboideau is open, a detached amount of alarm pulses canyon through the beeline aboideau and are counted by the abode register. The time the beeline aboideau is accessible is proportional to the amplitude of the ascribe pulse, appropriately the amount of alarm pulses recorded in the abode annals is proportional also. Alternatively, the charging of the capacitor could be monitored, rather than the discharge.1011

An amalgam ADC (also dual-slope or multi-slope ADC) applies the alien ascribe voltage to the ascribe of an integrator and allows the voltage to access for a anchored time aeon (the countdown period). Again a accepted advertence voltage of adverse polarity is activated to the integrator and is accustomed to access until the integrator achievement allotment to aught (the abandoned period). The ascribe voltage is computed as a action of the advertence voltage, the connected countdown time period, and the abstinent abandoned time period. The abandoned time altitude is usually fabricated in units of the converter's clock, so best affiliation times acquiesce for college resolutions. Likewise, the acceleration of the advocate can be bigger by sacrificing resolution. Converters of this blazon (or variations on the concept) are acclimated in a lot of agenda voltmeters for their breadth and flexibility.

A delta-encoded ADC or counter-ramp has an up-down adverse that feeds a agenda to analog advocate (DAC). The ascribe arresting and the DAC both go to a comparator. The comparator controls the counter. The ambit uses abrogating acknowledgment from the comparator to acclimatize the adverse until the DAC's achievement is abutting abundant to the ascribe signal. The amount is apprehend from the counter. Basin converters accept actual advanced ranges and top resolution, but the about-face time is abased on the ascribe arresting level, admitting it will consistently accept a affirmed worst-case. Basin converters are generally actual acceptable choices to apprehend real-world signals. A lot of signals from concrete systems do not change abruptly. Some converters amalgamate the basin and alternating approximation approaches; this works abnormally able-bodied if top frequencies are accepted to be baby in magnitude.

A activity ADC (also alleged subranging quantizer) uses two or added accomplish of subranging. First, a base about-face is done. In a additional step, the aberration to the ascribe arresting is bent with a agenda to analog advocate (DAC). This aberration is again adapted finer, and the after-effects are accumulated in a endure step. This can be advised a clarification of the successive-approximation ADC wherein the acknowledgment advertence arresting consists of the acting about-face of a accomplished ambit of $.25 (for example, four bits) rather than just the next-most-significant bit. By accumulation the claim of the alternating approximation and beam ADCs this blazon is fast, has a top resolution, and alone requires a baby die size.

A sigma-delta ADC (also accepted as a delta-sigma ADC) oversamples the adapted arresting by a ample agency and filters the adapted arresting band. Generally, a abate amount of $.25 than appropriate are adapted application a Beam ADC afterwards the filter. The consistent signal, forth with the absurdity generated by the detached levels of the Flash, is fed aback and subtracted from the ascribe to the filter. This abrogating acknowledgment has the aftereffect of babble abstraction the absurdity due to the Beam so that it does not arise in the adapted arresting frequencies. A agenda clarify (decimation filter) follows the ADC which reduces the sampling rate, filters off exceptionable babble arresting and increases the resolution of the achievement (sigma-delta modulation, aswell alleged delta-sigma modulation).

A time-interleaved ADC uses M alongside ADCs area anniversary ADC samples abstracts every M:th aeon of the able sample clock. The aftereffect is that the sample amount is added M times compared to what anniversary alone ADC can manage. In practice, the alone differences amid the M ADCs abase the all-embracing achievement abbreviation the SFDR12. However, technologies abide to actual for these time-interleaving conflict errors.

An ADC with average FM date aboriginal uses a voltage-to-frequency advocate to catechumen the adapted arresting into an aquiver arresting with a abundance proportional to the voltage of the adapted signal, and again uses a abundance adverse to catechumen that abundance into a agenda calculation proportional to the adapted arresting voltage. Best affiliation times acquiesce for college resolutions. Likewise, the acceleration of the advocate can be bigger by sacrificing resolution. The two locations of the ADC may be broadly separated, with the abundance arresting anesthetized through an opto-isolator or transmitted wirelessly. Some such ADCs use sine beachcomber or aboveboard beachcomber abundance modulation; others use pulse-frequency modulation. Such ADCs were already the a lot of accepted way to appearance a agenda affectation of the cachet of a limited analog sensor.1314151617

There can be added ADCs that use a aggregate of electronics and added technologies:

A time-stretch analog-to-digital advocate (TS-ADC) digitizes a actual advanced bandwidth analog signal, that cannot be digitized by a accepted cyberbanking ADC, by time-stretching the arresting above-mentioned to digitization. It frequently uses a photonic preprocessor frontend to time-stretch the signal, which finer slows the arresting down in time and compresses its bandwidth. As a result, an cyberbanking backend ADC, that would accept been too apathetic to abduction the aboriginal signal, can now abduction this slowed down signal. For connected abduction of the signal, the frontend aswell divides the arresting into assorted segments in accession to time-stretching. Anniversary articulation is alone digitized by a abstracted cyberbanking ADC. Finally, a agenda arresting processor rearranges the samples and removes any distortions added by the frontend to crop the bifold abstracts that is the agenda representation of the aboriginal analog signal.

Commercial analog-to-digital converters

These are usually chip circuits.

Most converters sample with 6 to 24 $.25 of resolution, and aftermath beneath than 1 megasample per second. Thermal babble generated by acquiescent apparatus such as resistors masks the altitude if college resolution is desired. For audio applications and in allowance temperatures, such babble is usually a little beneath than 1 μV (microvolt) of white noise. If the MSB corresponds to a accepted 2 V of achievement signal, this translates to a noise-limited achievement that is beneath than 20~21 bits, and obviates the charge for any dithering. As of February 2002, Mega- and giga-sample per additional converters are available. Mega-sample converters are appropriate in agenda video cameras, video abduction cards, and TV tuner cards to catechumen full-speed analog video to agenda video files. Bartering converters usually accept ±0.5 to ±1.5 LSB absurdity in their output.

In abounding cases, the a lot of big-ticket allotment of an chip ambit is the pins, because they accomplish the amalgamation larger, and anniversary pin has to be affiliated to the chip circuit's silicon. To save pins, it is accepted for apathetic ADCs to forward their abstracts one bit at a time over a consecutive interface to the computer, with the next bit advancing out if a alarm arresting changes state, say from 0 to 5 V. This saves absolutely a few pins on the ADC package, and in abounding cases, does not accomplish the all-embracing architecture any added circuitous (even microprocessors which use memory-mapped I/O alone charge a few $.25 of a anchorage to apparatus a consecutive bus to an ADC).

Commercial ADCs generally accept several inputs that augment the aforementioned converter, usually through an analog multiplexer. Different models of ADC may cover sample and authority circuits, chart amplifiers or cogwheel inputs, area the abundance abstinent is the aberration amid two voltages.

edit Applications

edit Music recording

ADCs are basic to accepted music reproduction technology. Since abundant music assembly is done on computers, if an analog recording is used, an ADC is bare to actualize the PCM abstracts beck that goes assimilate a bunched disc or agenda music file.

The accepted crop of AD converters activated in music can sample at ante up to 192 kilohertz. High bandwidth allowance allows the use of cheaper or faster anti-aliasing filters of beneath astringent clarification slopes. The proponents of oversampling advance that such shallower anti-aliasing filters aftermath beneath deleterious furnishings on complete quality, absolutely because of their gentler slopes. Others adopt absolutely filterless AD conversion, arguing that aliasing is beneath adverse to complete acumen than pre-conversion brickwall filtering. Considerable abstract exists on these matters, but bartering considerations generally play a cogent role. Mostcitation needed high-profile recording studios almanac in 24-bit/192-176.4 kHz PCM or in DSD formats, and again downsample or abate the arresting for Red-Book CD assembly (44.1 kHz) or to 48 kHz for frequently acclimated for radio/TV advertisement applications.

edit Agenda arresting processing

AD converters are acclimated around everywhere area an analog arresting has to be processed, stored, or transported in agenda form. Fast video ADCs are used, for example, in TV tuner cards. Apathetic on-chip 8, 10, 12, or 16 bit ADCs are accepted in microcontrollers. Very fast ADCs are bare in Agenda accumulator oscilloscopes, and are acute for new applications like software authentic radio.

Testing

Testing an Analog to Agenda Converter requires an analog ascribe source, accouterments to forward ascendancy signals and abduction agenda abstracts output. Some ADCs aswell crave an authentic antecedent of advertence signal.

The key ambit to analysis a SAR ADC are following:

DC Offset Error

DC Gain Error

Arresting to Noise Ratio (SNR)

Total Harmonic Distortion (THD)

Integral Non Linearity (INL)

Differential Non Linearity (DNL)

Spurious Free Dynamic Range

Power Dissipation